FIG. 1 shows a circuit diagram for a conventional current mirror circuit 10. The circuit includes an input current leg 12 and at least one output current leg 14. A current source 16 generates an input current Iin that is applied to the input current leg 12. The input current Iin is mirrored over to the output current leg 14 where an output current Iout is generated. The ratio of the magnitude of the output current to the input current is referred to as the mirroring ratio.
The circuit 10 is implemented using bipolar junction transistors (BJTs). The input current leg 12 includes a first BJT device 20 that is configured as a diode-connected device. The collector terminal of the first BJT device 20 is electrically coupled to the base terminal of the first BJT device 20, and the collector terminal of the first BJT device 20 is configured to receive the input current Iin from the current source 16. The emitter terminal of the first BJT device 20 is electrically coupled to a reference voltage supply node. For example, the reference voltage supply node may comprise a ground (Gnd) voltage node. The output current leg 14 includes a second BJT device 22. The base terminal of the second BJT device 22 is electrically coupled to the base terminal of the first BJT device 20. The emitter terminal of the second BJT device 22 is electrically coupled to the reference voltage supply node. The output current Tout in the output current leg 14 is generated at the collector terminal of the second BJT device 22.
FIG. 2 shows a circuit diagram for a conventional current mirror circuit 30. The circuit 30 differs from the circuit 10 in that the output current leg 14 includes a plurality of parallel connected second BJT devices 22(1)-22(n) forming a variable output transistor 22v. The base terminals of the second BJT devices 22(1)-22(n) are electrically coupled to the base terminal of the first BJT device 20. The emitter terminals of the second BJT devices 22(1)-22(n) are electrically coupled to the reference voltage supply node. The collector terminals of the second BJT devices 22(1)-22(n) are electrically coupled to a common output current node 32 through respective switches 34(1)-34(n). The output current Iout in the output current leg 14 is generated at the common output current node 32 as a sum of the currents generated at the collector terminals of the second BJT devices 22(1)-22(n). The magnitude of the output current Tout is accordingly dependent on the number of second BJT devices 22(1)-22(n) that are actuated using the corresponding switches 34(1)-34(n) electrically coupled between the collector terminal and the common output current node 32. As an example, a multibit digital control signal D can be used to selectively actuate the switches 34(1)-34(n).
FIG. 3 shows a circuit diagram for a conventional current mirror circuit 50. The circuit 50 differs from the circuit 30 in that multiple output current legs 14(1)-14(m) are provided. Each output current leg 14(1)-14(m) includes a variable output transistor 22v. The base terminals of the variable output transistors 22v(1)-22v(m) are electrically coupled to the base terminal of the first BJT device 20. The emitter terminals of the variable output transistors 22v(1)-22v(m) are electrically coupled to the reference voltage supply node. Each common output current node 32(1)-32(m) generates a distinct output current Iout(1)-Iout(m) for a corresponding current channel CH(1)-CH(m).
In many applications, such as for the generation of a precise amount of charge, it is important to exercise accurate control over the magnitude of the output current Tout. This can be a challenge, however, when the value of the multibit digital control signal D changes and one or more of the output current legs 14(1)-14(m) of a given channel CH are deactuated. There is a charge injection to the potential at the base terminals (Vbase) that introduces an error in output current generation. There is accordingly a need in the art for active base current compensation for the current mirror circuits of the type shown in FIGS. 2 and 3.